Horácio Cláudio de Campos Neto
AuthID: R-000-5ZS
41
TÃTULO: Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture
AUTORES: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias ;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTORES: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias ;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
42
TÃTULO: Enhancing stochastic computations via process variation
AUTORES: Duarte, RP; Véstias, M ; Neto, H;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications, FPL 2015 in 25th International Conference on Field Programmable Logic and Applications, FPL 2015
AUTORES: Duarte, RP; Véstias, M ; Neto, H;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications, FPL 2015 in 25th International Conference on Field Programmable Logic and Applications, FPL 2015
43
TÃTULO: FPGA Redundancy Recovery based on Partial Bitstreams for Multiple Partitions
AUTORES: Victor M G Goncalves Martins; Joao Gabriel Reis; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLICAÇÃO: 2015, FONTE: 16th IEEE Latin American Test Symposium (LATS) in 2015 16TH LATIN-AMERICAN TEST SYMPOSIUM (LATS)
AUTORES: Victor M G Goncalves Martins; Joao Gabriel Reis; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLICAÇÃO: 2015, FONTE: 16th IEEE Latin American Test Symposium (LATS) in 2015 16TH LATIN-AMERICAN TEST SYMPOSIUM (LATS)
INDEXADO EM: 
WOS
WOS44
TÃTULO: Enhancing Stochastic Computations via Process Variation
AUTORES: Rui Policarpo Duarte; Mario Vestias ; Horacio Neto;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
AUTORES: Rui Policarpo Duarte; Mario Vestias ; Horacio Neto;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
INDEXADO EM: WOS
WOS45
TÃTULO: Efficient implementation of a single-precision floating-point arithmetic unit on FPGA
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M ;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M ;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
46
TÃTULO: Trends of CPU, GPU and FPGA for high-performance computing
AUTORES: Vestias, M ; Neto, H;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
AUTORES: Vestias, M ; Neto, H;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
47
TÃTULO: Modeling and Simulation of a Many-Core Architecture Using SystemC
AUTORES: Ana Rita Silva; Wilson Jose; Horacio Neto; Mario Vestias ;
PUBLICAÇÃO: 2014, FONTE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
AUTORES: Ana Rita Silva; Wilson Jose; Horacio Neto; Mario Vestias ;
PUBLICAÇÃO: 2014, FONTE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
INDEXADO EM: WOS 
CrossRef
WOS CrossRef48
TÃTULO: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTORES: Wilson M José; Ana Rita Silva; Mário P Véstias ; Horácio C Neto;
PUBLICAÇÃO: 2014, FONTE: Analog Integrated Circuits and Signal Processing - Analog Integr Circ Sig Process, VOLUME: 82, NÚMERO: 1
AUTORES: Wilson M José; Ana Rita Silva; Mário P Véstias ; Horácio C Neto;
PUBLICAÇÃO: 2014, FONTE: Analog Integrated Circuits and Signal Processing - Analog Integr Circ Sig Process, VOLUME: 82, NÚMERO: 1
49
TÃTULO: Adaptive Network-on-Chip
AUTORES: Mário Véstias; Horácio C Neto;
PUBLICAÇÃO: 2014, VOLUME: 8
AUTORES: Mário Véstias; Horácio C Neto;
PUBLICAÇÃO: 2014, VOLUME: 8
INDEXADO EM: 
Scopus
Scopus50
TÃTULO: Hardware Design for Decimal Multiplication
AUTORES: Mário Véstias; Horácio C Neto;
PUBLICAÇÃO: 2014, VOLUME: 8
AUTORES: Mário Véstias; Horácio C Neto;
PUBLICAÇÃO: 2014, VOLUME: 8
INDEXADO EM: Scopus
Scopus