51
TITLE: System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures  Full Text
AUTHORS: Vestias, MP ; Neto, HC;
PUBLISHED: 2002, SOURCE: 13th IEEE International Workshop on Rapid System Prototyping in 13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS
INDEXED IN: WOS CrossRef
52
TITLE: Compilation increasing the scheduling scope for multi-memory-FPGA-based custom computing machines
AUTHORS: Cardoso, JMP ; Neto, HC;
PUBLISHED: 2001, SOURCE: 11th International Conference on Field-Programmable Logic and Applications, FPL 2001 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 2147
INDEXED IN: Scopus DBLP CrossRef
53
TITLE: An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs
AUTHORS: Cardoso, JMP ; Neto, HC;
PUBLISHED: 2000, SOURCE: IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) in VLSI: SYSTEMS ON A CHIP, VOLUME: 34
INDEXED IN: WOS DBLP CrossRef: 9
54
TITLE: Towards an automatic path from JavaTM bytecodes to hardware through high-level synthesis
AUTHORS: João M P Cardoso ; Horácio C Neto;
PUBLISHED: 1998, SOURCE: 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998
INDEXED IN: DBLP CrossRef: 6
55
TITLE: Bitwise encoding of finite state machines
AUTHORS: Jose Monteiro ; James Kukula; Srinivas Devadas; Horacio Neto;
PUBLISHED: 1994, SOURCE: Proceedings of the 7th International Conference on VLSI Design in Proceedings of the IEEE International Conference on VLSI Design
INDEXED IN: Scopus
IN MY: ORCID
Página 6 de 6. Total de resultados: 55.