Horácio Cláudio de Campos Neto
AuthID: R-000-5ZS
51
TÃTULO: A reconfigurable computing architecture using magnetic tunneling junction memories
AUTORES: Silva, V; Fernandes, J ; Vestias, M ; Neto, H;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
AUTORES: Silva, V; Fernandes, J ; Vestias, M ; Neto, H;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
52
TÃTULO: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTORES: Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2013, FONTE: Embedded Systems Design with FPGAs
AUTORES: Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2013, FONTE: Embedded Systems Design with FPGAs
INDEXADO EM: 
Scopus
Scopus NO MEU: 
ORCID
ORCID53
TÃTULO: Very low resource table-based FPGA evaluation of elementary functions
AUTORES: Horacio C Neto; Mario P Vestias ;
PUBLICAÇÃO: 2013, FONTE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
AUTORES: Horacio C Neto; Mario P Vestias ;
PUBLICAÇÃO: 2013, FONTE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
INDEXADO EM: 
WOS
WOS54
TÃTULO: ANALYSIS OF MATRIX MULTIPLICATION ON HIGH DENSITY VIRTEX-7 FPGA
AUTORES: Wilson Jose; Ana Rita Silva; Horacio Neto; Mario Vestias ;
PUBLICAÇÃO: 2013, FONTE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
AUTORES: Wilson Jose; Ana Rita Silva; Horacio Neto; Mario Vestias ;
PUBLICAÇÃO: 2013, FONTE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
INDEXADO EM: WOS
WOS55
TÃTULO: A RECONFIGURABLE COMPUTING ARCHITECTURE USING MAGNETIC TUNNELING JUNCTION MEMORIES
AUTORES: Victor Silva; Jorge Fernandes; Mario Vestias ; Horacio Neto;
PUBLICAÇÃO: 2013, FONTE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
AUTORES: Victor Silva; Jorge Fernandes; Mario Vestias ; Horacio Neto;
PUBLICAÇÃO: 2013, FONTE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
INDEXADO EM: WOS
WOS56
TÃTULO: Decimal Division Using the Newton–Raphson Method and Radix-1000 Arithmetic
AUTORES: Mário P Véstias; Horácio C Neto;
PUBLICAÇÃO: 2012, FONTE: Embedded Systems Design with FPGAs
AUTORES: Mário P Véstias; Horácio C Neto;
PUBLICAÇÃO: 2012, FONTE: Embedded Systems Design with FPGAs
57
TÃTULO: Non-Volane Memory Circuits for FIMS and TAS Writing Techniques on Magnetic Tunnelling Junctions
AUTORES: Victor Silva; Mario P Vestias ; Horacio C Neto; Jorge R Fernandes;
PUBLICAÇÃO: 2012, FONTE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
AUTORES: Victor Silva; Mario P Vestias ; Horacio C Neto; Jorge R Fernandes;
PUBLICAÇÃO: 2012, FONTE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXADO EM: WOS
WOS58
TÃTULO: Dynamically reconfigurable networks-on-chip using runtime adaptive routers
AUTORES: Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2010, FONTE: Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
AUTORES: Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2010, FONTE: Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
INDEXADO EM: Scopus
Scopus NO MEU: ORCID
ORCID59
TÃTULO: Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
AUTORES: Mário P Véstias; Horácio C Neto;
PUBLICAÇÃO: 2010, FONTE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
AUTORES: Mário P Véstias; Horácio C Neto;
PUBLICAÇÃO: 2010, FONTE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
60
TÃTULO: Data-driven regular reconfigurable arrays: Design space exploration and mapping Full Text
AUTORES: Ferreira, R; Cardoso, JMP ; Toledo, A; Neto, HC;
PUBLICAÇÃO: 2005, FONTE: 5th International Workshop on Embedded Computer Systems - Architectures, Modeling,, and Simulation in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, VOLUME: 3553
AUTORES: Ferreira, R; Cardoso, JMP ; Toledo, A; Neto, HC;
PUBLICAÇÃO: 2005, FONTE: 5th International Workshop on Embedded Computer Systems - Architectures, Modeling,, and Simulation in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, VOLUME: 3553
