Horácio Cláudio de Campos Neto
AuthID: R-000-5ZS
61
TÃTULO: An efficient, low resource, architecture for backpropagation neural networks
AUTORES: Domingos, PO; Neto, HC;
PUBLICAÇÃO: 2005, FONTE: International Workshop on Applied Reconfigurable Computing 2005, ARC 2005 in ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005
AUTORES: Domingos, PO; Neto, HC;
PUBLICAÇÃO: 2005, FONTE: International Workshop on Applied Reconfigurable Computing 2005, ARC 2005 in ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005
INDEXADO EM: 
Scopus
Scopus NO MEU: 
ORCID
ORCID62
TÃTULO: An environment for exploring data-driven architectures
AUTORES: Ferreira, R; Cardoso, JMP ; Neto, HC;
PUBLICAÇÃO: 2004, FONTE: 14th International Conference on Field-Programmable Logic and Applications in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 3203
AUTORES: Ferreira, R; Cardoso, JMP ; Neto, HC;
PUBLICAÇÃO: 2004, FONTE: 14th International Conference on Field-Programmable Logic and Applications in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 3203
63
TÃTULO: A modular reconfigurable architecture for efficient fault simulation in digital circuits
AUTORES: Augusto, JS ; Almeida, CB; Neto, HCC;
PUBLICAÇÃO: 2003, FONTE: 13th International Conference on Field-Programmable Logic and Applications (FPL 2003) in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 2778
AUTORES: Augusto, JS ; Almeida, CB; Neto, HCC;
PUBLICAÇÃO: 2003, FONTE: 13th International Conference on Field-Programmable Logic and Applications (FPL 2003) in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 2778
64
TÃTULO: DALI: A methodology for the co-design of dataflow applications on hardware/software architectures
AUTORES: Vestias, MP ; Neto, HC;
PUBLICAÇÃO: 2003, FONTE: 16th Symposium on Integrated Circuits and Systems Design in 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS
AUTORES: Vestias, MP ; Neto, HC;
PUBLICAÇÃO: 2003, FONTE: 16th Symposium on Integrated Circuits and Systems Design in 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS
INDEXADO EM: 
WOS
WOS65
TÃTULO: DALI: A methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]
AUTORES: Véstias, MP; Neto, HC;
PUBLICAÇÃO: 2003, FONTE: 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003 in Proceedings - 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003
AUTORES: Véstias, MP; Neto, HC;
PUBLICAÇÃO: 2003, FONTE: 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003 in Proceedings - 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003
INDEXADO EM: Scopus
Scopus NO MEU: ORCID
ORCID66
TÃTULO: System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures Full Text
AUTORES: Vestias, MP ; Neto, HC;
PUBLICAÇÃO: 2002, FONTE: 13th IEEE International Workshop on Rapid System Prototyping in 13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, VOLUME: 2002-January
AUTORES: Vestias, MP ; Neto, HC;
PUBLICAÇÃO: 2002, FONTE: 13th IEEE International Workshop on Rapid System Prototyping in 13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, VOLUME: 2002-January
67
TÃTULO: Compilation increasing the scheduling scope for multi-memory-FPGA-based custom computing machines
AUTORES: Cardoso, JMP ; Neto, HC;
PUBLICAÇÃO: 2001, FONTE: 11th International Conference on Field-Programmable Logic and Applications, FPL 2001 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 2147
AUTORES: Cardoso, JMP ; Neto, HC;
PUBLICAÇÃO: 2001, FONTE: 11th International Conference on Field-Programmable Logic and Applications, FPL 2001 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 2147
68
TÃTULO: An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs
AUTORES: Cardoso, JMP ; Neto, HC;
PUBLICAÇÃO: 2000, FONTE: IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) in VLSI: SYSTEMS ON A CHIP, VOLUME: 34
AUTORES: Cardoso, JMP ; Neto, HC;
PUBLICAÇÃO: 2000, FONTE: IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) in VLSI: SYSTEMS ON A CHIP, VOLUME: 34
69
TÃTULO: Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system
AUTORES: Joéo M P Cardoso ; Horácio C Neto;
PUBLICAÇÃO: 1999, FONTE: Proceedings - 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999
AUTORES: Joéo M P Cardoso ; Horácio C Neto;
PUBLICAÇÃO: 1999, FONTE: Proceedings - 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999
70
TÃTULO: Towards an automatic path from JavaTM bytecodes to hardware through high-level synthesis
AUTORES: João M P Cardoso ; Horácio C Neto;
PUBLICAÇÃO: 1998, FONTE: 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998
AUTORES: João M P Cardoso ; Horácio C Neto;
PUBLICAÇÃO: 1998, FONTE: 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998
