161
TITLE: Performance Analysis with Cache-Aware Roofline Model in Intel Advisor
AUTHORS: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXED IN: DBLP
IN MY: DBLP
162
TITLE: Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model
AUTHORS: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXED IN: DBLP
IN MY: DBLP
163
TITLE: Gender parity or "informed consent" in media representations of science and technology? A corpus-based discourse approach
AUTHORS: Sousa, APD; Silva, J;
PUBLISHED: 2017, SOURCE: Lodz Papers in Pragmatics, VOLUME: 13, ISSUE: 1
INDEXED IN: Scopus
164
TITLE: GPU Parallelization of HEVC In-Loop Filters
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 45, ISSUE: 6
INDEXED IN: WOS CrossRef
165
TITLE: Arithmetical Improvement of the Round-Off for Cryptosystems in High-Dimensional Lattices
AUTHORS: Paulo Martins; Julien Eynard; Jean Claude Bajard; Leonel Sousa;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON COMPUTERS, VOLUME: 66, ISSUE: 12
INDEXED IN: WOS DBLP
IN MY: DBLP
166
TITLE: Energy-efficient motion estimation with approximate arithmetic
AUTHORS: Roger Endrigo Carvalho Porto; Luciano Volcan Agostini; Bruno Zatt; Marcelo Schiavon Porto; Nuno Roma; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 19th IEEE International Workshop on Multimedia Signal Processing, MMSP 2017, Luton, United Kingdom, October 16-18, 2017
INDEXED IN: DBLP
IN MY: DBLP
167
TITLE: A stochastic number representation for fully homomorphic cryptography
AUTHORS: Paulo Martins; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 2017 IEEE International Workshop on Signal Processing Systems, SiPS 2017 in 2017 IEEE International Workshop on Signal Processing Systems, SiPS 2017, Lorient, France, October 3-5, 2017, VOLUME: 2017-October
INDEXED IN: Scopus DBLP
IN MY: DBLP
170
TITLE: Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
AUTHORS: Nicolas Denoyelle; Brice Goglin; Aleksandar Ilic; Emmanuel Jeannot; Leonel Sousa;
PUBLISHED: 2017, SOURCE: High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation - 8th International Workshop, PMBS 2017, Denver, CO, USA, November 13, 2017, Proceedings, VOLUME: 10724
INDEXED IN: DBLP
IN MY: DBLP
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