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Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs

AuthID
P-008-YB7

Author(s)

Monteiro, J

Devadas, S

Tipo de Documento

Proceedings Paper

Year published

1995

Publicado

in Proceedings of the International Symposium on Low Power Design

Páginas: 33-38

Conference

Proceedings of the 1995 International Symposium on Low Power Design, Date: 23 April 1995 through 26 April 1995, Location: Dana Point, CA, USA, Patrocinadores: ACM-SIGDA;IEEE-CAS

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Scopus^®

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Publication Identifiers

SCOPUS: 2-s2.0-0029192470

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Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs

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Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs

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