Sequential Logic Optimization for Low Power Using Input-Disabling Precomputation Architectures

AuthID
P-001-8BX
3
Author(s)
Ghosh, A
Tipo de Documento
Article
Year published
1998
Publicado
in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, ISSN: 0278-0070
Volume: 17, Número: 3, Páginas: 279-284 (6)
Indexing
Publication Identifiers
SCOPUS: 2-s2.0-0003017407
Wos: WOS:000074713900008
Source Identifiers
ISSN: 0278-0070
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