Bayesian Model Fusion: Enabling Test Cost Reduction of Analog/Rf Circuits via Wafer-Level Spatial Variation Modeling

AuthID
P-00J-XN4
6
Author(s)
Zhang, SH
·
Li, X
·
Blanton, RD
·
Carulli, JM
·
Butler, KM
Tipo de Documento
Proceedings Paper
Year published
2014
Publicado
in 2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC) in International Test Conference Proceedings, ISSN: 1089-3539
Volume: 2015-February, Páginas: 1-10 (10)
Conference
45Th Ieee International Test Conference (Itc), Date: OCT 21-23, 2014, Location: Seattle, DC, Patrocinadores: IEEE Comp Soc, Test Technol Tech Council, IEEE, IEEE Philadelphia Sect
Indexing
Publication Identifiers
DBLP: conf/itc/ZhangLBSCB14
SCOPUS: 2-s2.0-84954288409
Wos: WOS:000370703300053
Source Identifiers
ISSN: 1089-3539
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