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Sensitivity Aware Nsga-Ii Based Pareto Front Generation for the Optimal Sizing of Analog Circuits

AuthID
P-00K-NYV

Author(s)

Kchaou, OB

Garbaya, A

Kotti, M

Pereira, P

Fakhfakh, M

Fino, MH

Tipo de Documento

Article

Year published

2016

Publicado

in INTEGRATION-THE VLSI JOURNAL, ISSN: 0167-9260

Volume: 55, Páginas: 220-226 (7)

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Publication Identifiers

DOI: 10.1016/j.vlsi.2016.07.001

SCOPUS: 2-s2.0-84978909882

Wos: WOS:000386401500020

Source Identifiers

ISSN: 0167-9260

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Sensitivity Aware Nsga-Ii Based Pareto Front Generation for the Optimal Sizing of Analog Circuits

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