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A 0.14-To-0.29-Pj/Bit 14-Gbaud/S Trimodal (Nrz/Pam-4/Pam-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (Bbcdr) in 28-Nm Cmos

AuthID
P-00R-NVG

Author(s)

Zhao, X

Chen, Y

Mak, PI

Martins, RP

Tipo de Documento

Proceedings Paper

Year published

2019

Publicado

in Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption

Páginas: 229-232

Conference

15Th Annual Ieee Asia Pacific Conference on Circuits and Systems, Apccas 2019, Date: 11 November 2019 through 14 November 2019, Patrocinadores: IEEE;IEEE Circuits and Systems (CAS) Society

Indexing

Scopus^®

Google Scholar^®

Publication Identifiers

DOI: 10.1109/apccas47518.2019.8953158

SCOPUS: 2-s2.0-85078696897

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A 0.14-To-0.29-Pj/Bit 14-Gbaud/S Trimodal (Nrz/Pam-4/Pam-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (Bbcdr) in 28-Nm Cmos

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A 0.14-To-0.29-Pj/Bit 14-Gbaud/S Trimodal (Nrz/Pam-4/Pam-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (Bbcdr) in 28-Nm Cmos

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