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Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level

AuthID
P-002-ZWW

Author(s)

Aksoy, L

Lazzari, C

Costa, E

Flores, P

Monteiro, J

Tipo de Documento

Proceedings Paper

Year published

2011

Publicado

in 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) in IEEE International Symposium on Circuits and Systems, ISSN: 0271-4302

Páginas: 2737-2740 (4)

Conference

Ieee International Symposium on Circuits and Systems (Iscas), Date: MAY 15-18, 2011, Location: Rio de Janeiro, BRAZIL, Patrocinadores: IEEE

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Publication Identifiers

DOI: 10.1109/iscas.2011.5938171

SCOPUS: 2-s2.0-79960853068

Wos: WOS:000297265303032

Source Identifiers

ISSN: 0271-4302

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Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level

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Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level

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