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Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded Plds

AuthID
P-000-3EA

Author(s)

Aguiar, RL

Figueiredo, M

Document Type

Article

Year published

2005

Published

in ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, ISSN: 0925-1030

Volume: 43, Issue: 2, Pages: 159-170 (12)

Conference

10Th Ieee International Conference on Electronics, Circuits and Systems, Date: DEC 14-17, 2003, Location: Sharjah, U ARAB EMIRATES, Sponsors: IEEE, IEEE Circuits & Syst Soc, Univ Sharjah, Etisalat Coll Engn, Emirates Telecommun Corp, Amer Univ Sharjah, Thuraya Satellite Telecommun Co, Dubai Elect & Water Author

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Publication Identifiers

DOI: 10.1007/s10470-005-6789-y

Wos: WOS:000228979700005

Source Identifiers

ISSN: 0925-1030

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Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded Plds

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