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A 167-Μ W 71.7-Db Sfdr 2.4-Ghz Ble Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D Vco

AuthID
P-017-4MM

Author(s)

Shao, HJ

Martins, RP

Mak, PI

Document Type

Article in Press

Year published

2024

Published

in IEEE JOURNAL OF SOLID-STATE CIRCUITS, ISSN: 0018-9200

Indexing

Wos^®

Scopus^®

Google Scholar^®

Publication Identifiers

DOI: 10.1109/jssc.2024.3462093

Scopus: 2-s2.0-85205714132

Wos: WOS:001329040300001

Source Identifiers

ISSN: 0018-9200

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A 167-Μ W 71.7-Db Sfdr 2.4-Ghz Ble Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D Vco

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A 167-Μ W 71.7-Db Sfdr 2.4-Ghz Ble Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D Vco

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