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An 80W Single-Inductor Dc-Dc Architecture for Simultaneous Flash Charging and Dual-Output Pol Supply with 92.1% Peak Efficiency from 15V-To-28V Input to 12.6V/3.3V/1V Outputs Using 1.3Mm3 Inductor

AuthID
P-017-FAD

Author(s)

Zhang, XJ

Li, XM

Document Type

Proceedings Paper

Year published

2024

Published

in 2024 50TH IEEE EUROPEAN SOLID-STATE ELECTRONICS RESEARCH CONFERENCE, ESSERC 2024 in Proceedings of the European Solid-State Circuits Conference, ISSN: 1930-8833

Pages: 61-64 (4)

Conference

50Th Ieee European Solid-State Electronics Research Conference (Esserc), Date: SEP 09-12, 2024, Location: Bruges, BELGIUM

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Publication Identifiers

DOI: 10.1109/esserc62670.2024.10719468

Scopus: 2-s2.0-85208435182

Wos: WOS:001349548800017

Source Identifiers

ISSN: 1930-8833

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An 80W Single-Inductor Dc-Dc Architecture for Simultaneous Flash Charging and Dual-Output Pol Supply with 92.1% Peak Efficiency from 15V-To-28V Input to 12.6V/3.3V/1V Outputs Using 1.3Mm3 Inductor

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An 80W Single-Inductor Dc-Dc Architecture for Simultaneous Flash Charging and Dual-Output Pol Supply with 92.1% Peak Efficiency from 15V-To-28V Input to 12.6V/3.3V/1V Outputs Using 1.3Mm3 Inductor

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