A 97.8 Gops/W Fpga-Based Residual-Block-Aware Cnn Accelerator Featuring Multi-Clock Pw2 Pipeline and Adaptive-Resolution Quantization

AuthID
 P-017-P92
6
Author(s)
Li, JX
·
Li, K
·
Un, KF
·
Yu, WH
·
Mak, PI
Document Type
Article in Press
Year published
2024
Published
in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN: 1549-8328
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Wos®
Scopus®
Google Scholar®
Publication Identifiers
Scopus: 2-s2.0-85210960901
Wos: WOS:001367632400001
Source Identifiers
ISSN: 1549-8328
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