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TITLE: Pegasus: Performance Engineering for Software Applications Targeting HPC Systems  Full Text
AUTHORS: Pinto, P; Bispo, J ; Cardoso, J ; Barbosa, JG ; Gadioli, D; Palermo, G; Martinovic, J; Golasowski, M; Slaninova, K; Cmar, R; Silvano, C;
PUBLISHED: 2022, SOURCE: IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, VOLUME: 48, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef: 1
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TITLE: A Binary Translation Framework for Automated Hardware Generation  Full Text
AUTHORS: Paulino, N ; Bispo, J ; Ferreira, JC ; Cardoso, JMP ;
PUBLISHED: 2021, SOURCE: IEEE MICRO, VOLUME: 41, ISSUE: 4
INDEXED IN: WOS DBLP CrossRef: 1
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3
TITLE: Building Beyond HLS: Graph Analysis and Others
AUTHORS: Pedro Filipe Silva; João Bispo ; Nuno Miguel Cardanha Paulino ;
PUBLISHED: 2021, SOURCE: CoRR, VOLUME: abs/2104.02676
INDEXED IN: DBLP
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TITLE: FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example
AUTHORS: Silva, Pedro Filipe; Bispo, Joao ; Paulino, Nuno ;
PUBLISHED: 2021, SOURCE: 20th International Conference on Field-Programmable Technology (ICFPT) in 2021 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT)
INDEXED IN: Scopus WOS DBLP CrossRef
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TITLE: Multi-language static code analysis on the LARA framework
AUTHORS: Gil Teixeira; João Bispo ; Filipe F Correia ;
PUBLISHED: 2021, SOURCE: SOAP@PLDI 2021: Proceedings of the 10th ACM SIGPLAN International Workshop on the State Of the Art in Program Analysis, Virtual Event, Canada, 22 June, 2021
INDEXED IN: Scopus DBLP CrossRef
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TITLE: On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators
AUTHORS: Tiago Santos; Nuno Paulino ; João Bispo ; João M P Cardoso ; João Canas Ferreira ;
PUBLISHED: 2021, SOURCE: 20th International Conference on Field-Programmable Technology, ICFPT 2021 in International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021
INDEXED IN: Scopus DBLP CrossRef
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TITLE: Clava: C/C plus plus source-to-source compilation using LARA
AUTHORS: Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2020, SOURCE: SOFTWAREX, VOLUME: 12
INDEXED IN: Scopus WOS DBLP CrossRef: 5
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TITLE: Compilation of MATLAB computations to CPU/GPU via C/OpenCL generation  Full Text
AUTHORS: Reis, L; Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2020, SOURCE: CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, VOLUME: 32, ISSUE: 22
INDEXED IN: Scopus WOS DBLP CrossRef
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TITLE: Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework
AUTHORS: Paulino, N ; Ferreira, JC ; Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2020, SOURCE: 30th International Conference on Field-Programmable Logic and Applications (FPL) in 2020 30TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
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