(Shawn) D. Blanton
AuthID: R-00H-46F
1
TITLE: IC Protection Against JTAG-Based Attacks Full Text
AUTHORS: Xuanle L Ren; Francisco Pimentel Torres; Blanton, RD; Vitor Grade Tavares ;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 38, ISSUE: 1
AUTHORS: Xuanle L Ren; Francisco Pimentel Torres; Blanton, RD; Vitor Grade Tavares ;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 38, ISSUE: 1
2
TITLE: Detection of IJTAG Attacks Using LDPC-based Feature Reduction and Machine Learning
AUTHORS: Xuanle L Ren; (Shawn) D S Blanton; Vitor Grade Tavares ;
PUBLISHED: 2018, SOURCE: 23rd IEEE European Test Symposium (ETS) in 2018 23RD IEEE EUROPEAN TEST SYMPOSIUM (ETS), VOLUME: 2018-May
AUTHORS: Xuanle L Ren; (Shawn) D S Blanton; Vitor Grade Tavares ;
PUBLISHED: 2018, SOURCE: 23rd IEEE European Test Symposium (ETS) in 2018 23RD IEEE EUROPEAN TEST SYMPOSIUM (ETS), VOLUME: 2018-May
3
TITLE: A Learning-based Approach to Secure JTAG against Unseen Scan-based Attacks
AUTHORS: Xuanle L Ren ; (Shawn) D Blanton; Vitor Grade Tavares ;
PUBLISHED: 2016, SOURCE: IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), VOLUME: 2016-September
AUTHORS: Xuanle L Ren ; (Shawn) D Blanton; Vitor Grade Tavares ;
PUBLISHED: 2016, SOURCE: IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), VOLUME: 2016-September
4
TITLE: Detection of Illegitimate Access to JTAG via Statistical Learning in Chip
AUTHORS: Xuanle L Ren; Vitor Grade Tavares ; (Shawn) D Blanton;
PUBLISHED: 2015, SOURCE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
AUTHORS: Xuanle L Ren; Vitor Grade Tavares ; (Shawn) D Blanton;
PUBLISHED: 2015, SOURCE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
INDEXED IN: 
Scopus 
WOS
Scopus WOS5
TITLE: Bayesian Model Fusion: Enabling Test Cost Reduction of Analog/RF Circuits via Wafer-level Spatial Variation Modeling Full Text
AUTHORS: Shanghang H Zhang; Xin Li; (Shawn) D Blanton; Jose Machado da Silva ; John M Carulli; Kenneth M Butler;
PUBLISHED: 2014, SOURCE: 45th IEEE International Test Conference (ITC) in 2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), VOLUME: 2015-February
AUTHORS: Shanghang H Zhang; Xin Li; (Shawn) D Blanton; Jose Machado da Silva ; John M Carulli; Kenneth M Butler;
PUBLISHED: 2014, SOURCE: 45th IEEE International Test Conference (ITC) in 2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), VOLUME: 2015-February
