João Carlos Viegas Martins Bispo


AuthID: R-000-6X6

Confirmed Publications: 70



51
TITLE: Techniques for efficient MATLAB-to-C compilation
AUTHORS: João Bispo ; Luís Reis ; João M P Cardoso ;
PUBLISHED: 2015, SOURCE: 2nd ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming, ARRAY 2015 in Proceedings of the 2nd ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming, ARRAY@PLDI, Portland, OR, USA, June 15 - 17, 2015
INDEXED IN: Scopus DBLP CrossRef: 4
IN MY: ORCID | DBLP
52
TITLE: Transparent Acceleration of Program Execution Using Reconfigurable Hardware  Full Text
AUTHORS: Paulino, N ; Ferreira, JC ; Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2015, SOURCE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
INDEXED IN: Scopus WOS DBLP CrossRef: 6
IN MY: ORCID | DBLP
53
TITLE: Multi-target c code generation from MATLAB
AUTHORS: Bispo, J ; Reis, L ; Cardoso, JMP ;
PUBLISHED: 2014, SOURCE: 1st ACM SIGPLAN International Workshop on Libraries, Languages and Compilers for Array Programming, ARRAY 2014 - Part of PLDI 2014 in Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
INDEXED IN: Scopus DBLP CrossRef: 5
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54
TITLE: Hardware pipelining of repetitive patterns in processor instruction traces
AUTHORS: Bispo, J ; Cardoso, JMP ; Monteiro, J ;
PUBLISHED: 2013, SOURCE: Journal of Integrated Circuits and Systems, VOLUME: 8, ISSUE: 1
INDEXED IN: Scopus
IN MY: ORCID
55
TITLE: The MATISSE MATLAB Compiler
AUTHORS: Joao Bispo ; Pedro Pinto ; Ricardo Nobre ; Tiago Carvalho; Joao M P Cardoso ; Pedro C Diniz ;
PUBLISHED: 2013, SOURCE: 11th IEEE International Conference on Industrial Informatics (INDIN) in 2013 11TH IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL INFORMATICS (INDIN)
INDEXED IN: Scopus WOS DBLP CrossRef: 6
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56
TITLE: Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units  Full Text
AUTHORS: Bispo, J ; Paulino, N ; Cardoso, JMP ; Ferreira, JC ;
PUBLISHED: 2013, SOURCE: International Journal of Reconfigurable Computing, VOLUME: 2013
INDEXED IN: Scopus DBLP CrossRef: 6
IN MY: ORCID | DBLP
57
TITLE: Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
AUTHORS: Joao Bispo ; Nuno Paulino ; Joao M P Cardoso ; Joao C Ferreira ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOLUME: 9, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef: 10
IN MY: ORCID | DBLP
58
TITLE: Hardware pipelining of runtime-detected loops
AUTHORS: João Bispo ; João M P Cardoso ; José Monteiro ;
PUBLISHED: 2012, SOURCE: 2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012 in 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012, Brasilia, Brazil, August 30 - September 2, 2012
INDEXED IN: Scopus DBLP CrossRef: 1
IN MY: ORCID | DBLP
59
TITLE: From Instruction Traces to Specialized Reconfigurable Arrays
AUTHORS: João Bispo ; Nuno Miguel Cardanha Paulino ; João M P Cardoso ; João Canas Ferreira ;
PUBLISHED: 2011, SOURCE: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 in 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011
INDEXED IN: Scopus DBLP CrossRef: 6
IN MY: ORCID | DBLP
60
TITLE: Techniques for Dynamically Mapping Computations to Coprocessors
AUTHORS: João Bispo ; João M P Cardoso ;
PUBLISHED: 2011, SOURCE: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 in 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011
INDEXED IN: Scopus DBLP CrossRef: 1
IN MY: ORCID | DBLP
Página 6 de 7. Total de resultados: 70.

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