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TÍTULO: An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios  Full Text
AUTORES: Mario Lopes Ferreira; Joao Canas Ferreira ;
FONTE: ELECTRONICS, VOLUME: 8, NÚMERO: 1, PUBLICAÇÃO: 2019
INDEXADO EM: Scopus WOS
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TÍTULO: Dynamic Partial Reconfiguration of Customized Single-Row Accelerators  Full Text
AUTORES: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
FONTE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 27, NÚMERO: 1, PUBLICAÇÃO: 2019
INDEXADO EM: WOS DBLP CrossRef
3
TÍTULO: A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems
AUTORES: Mário Lopes Ferreira ; João Canas Ferreira ; Michael Hübner;
FONTE: 14th International Symposium on Applied Reconfigurable Computing, ARC 2018 in Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, VOLUME: 10824, PUBLICAÇÃO: 2018
INDEXADO EM: Scopus DBLP CrossRef
NO MEU: DBLP
4
TÍTULO: An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem  Full Text
AUTORES: Pedro Vieira dos Santos; Jose Carlos Alves ; Joao Canas Ferreira ;
FONTE: 18th Euromicro Conference on Digital System Design (DSD) in MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 58, PUBLICAÇÃO: 2018
INDEXADO EM: Scopus WOS DBLP CrossRef
NO MEU: ORCID | DBLP
6
TÍTULO: Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing
AUTORES: Helder H Avelar ; João Canas Ferreira ;
FONTE: 21st Euromicro Conference on Digital System Design, DSD 2018 in 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018, PUBLICAÇÃO: 2018
INDEXADO EM: Scopus DBLP
NO MEU: DBLP
7
TÍTULO: Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator
AUTORES: Mario Lopes Ferreira; Joao Canas Ferreira ;
FONTE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLUME: 2018-May, PUBLICAÇÃO: 2018
INDEXADO EM: Scopus WOS DBLP CrossRef
NO MEU: DBLP
8
TÍTULO: Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices
AUTORES: Joao Lopes; Diogo Sousa; Joao Canas Ferreira ;
FONTE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2017 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), PUBLICAÇÃO: 2017
INDEXADO EM: WOS DBLP CrossRef
NO MEU: ORCID | DBLP
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TÍTULO: FPGA-based Implementation of a Frequency Spreading FBMC-OQAM Baseband Modulator
AUTORES: Miguel Carvalho; Mario Lopes Ferreira ; Joao Canas Ferreira ;
FONTE: 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) in 2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), PUBLICAÇÃO: 2017
INDEXADO EM: WOS DBLP CrossRef
NO MEU: ORCID | DBLP
10
TÍTULO: Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces  Full Text
AUTORES: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
FONTE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 25, NÚMERO: 1, PUBLICAÇÃO: 2017
INDEXADO EM: Scopus WOS DBLP CrossRef: 1
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