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João Paulo de Castro Canas Ferreira
AuthID:
R-000-7A5
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Proceedings Paper (57)
Article (28)
Book Chapter (7)
Editorial Material (3)
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Results:
10
20
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50
Confirmed Publications: 95
81
TITLE:
Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer
AUTHORS:
João Canas Ferreira
;
Miguel M Silva
;
PUBLISHED:
2005
,
SOURCE:
19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
in
19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA,
VOLUME:
2005
INDEXED IN:
Scopus
DBLP
CrossRef
:
4
IN MY:
ORCID
|
ResearcherID
|
DBLP
82
TITLE:
Using a tightly-coupled pipeline in dynamically reconfigurable platform FPGAs
AUTHORS:
Silva, ML
;
Ferreira, JC
;
PUBLISHED:
2005
,
SOURCE:
8th Euromicro Conference on Digital System Design
in
DSD 2005: 8th Euromicro Conference on Digital System Design, Proceedings,
VOLUME:
2005
INDEXED IN:
Scopus
WOS
DBLP
CrossRef
IN MY:
ORCID
|
ResearcherID
|
DBLP
83
TITLE:
A development support system for applications that use dynamically reconfigurable hardware
AUTHORS:
Ferreira, JC
;
Matos, JS
;
PUBLISHED:
2004
,
SOURCE:
14th International Conference on Field-Programmable Logic and Applications
in
FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS,
VOLUME:
3203
INDEXED IN:
Scopus
WOS
DBLP
IN MY:
ORCID
|
ResearcherID
|
DBLP
84
TITLE:
FAFNER-Accelerating Nesting Problems with FPGAs
AUTHORS:
José Carlos Alves
;
João Canas Ferreira
; Albuquerque, C;
José Fernando Oliveira
;
José Soeiro Ferreira
;
José Silva Matos
;
PUBLISHED:
1999
,
SOURCE:
Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCMM 1999)
in
7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA
INDEXED IN:
Scopus
DBLP
CrossRef
IN MY:
ORCID
|
DBLP
85
TITLE:
A prototype system for rapid application development using dynamically reconfigurable hardware
AUTHORS:
Ferreira, JC
;
Matos, JS
;
PUBLISHED:
1998
,
SOURCE:
IEEE Symposium on FPGAs for Custom Computing Machines
in
IEEE SYMPOSIUM ON FPGAS FOR CUSTOM COMPUTING MACHINES, PROCEEDINGS
INDEXED IN:
WOS
DBLP
CrossRef
IN MY:
ORCID
|
ResearcherID
|
DBLP
86
TITLE:
Flexible hardware acceleration for nesting problems
AUTHORS:
João Canas Ferreira
;
José Carlos Alves
; Albuquerque, C;
José Fernando Oliveira
;
José Soeiro Ferreira
;
José Silva Matos
;
PUBLISHED:
1998
,
SOURCE:
Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
in
5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998 ,
VOLUME:
1
INDEXED IN:
Scopus
DBLP
CrossRef
:
1
IN MY:
ORCID
|
DBLP
87
TITLE:
Mixed hardware/software applications on dynamically reconfigurable hardware
AUTHORS:
João Canas Ferreira
;
José Silva Matos
;
PUBLISHED:
1998
,
SOURCE:
Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
in
5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998 ,
VOLUME:
1
INDEXED IN:
Scopus
DBLP
CrossRef
IN MY:
ORCID
|
DBLP
88
TITLE:
AN APPROACH TO TESTABILITY IMPROVEMENT OF MIXED-SIGNAL BOARDS
AUTHORS:
MATOS, JS
;
FERREIRA, JC
; LEAO, AC;
PUBLISHED:
1994
,
SOURCE:
1994 IEEE International Symposium on Circuits and Systems
in
1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: NONLINEAR CIRCUITS AND SYSTEMS (NCS) - NEURAL SYSTEMS (NEU)
INDEXED IN:
WOS
IN MY:
ORCID
|
ResearcherID
89
TITLE:
An Approach to Testability Improvement of Mixed-Signal Boards
AUTHORS:
José Silva Matos
;
João Canas Ferreira
; Ana C Leão; José Machado da Silva;
PUBLISHED:
1994
,
SOURCE:
1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994
INDEXED IN:
DBLP
IN MY:
ORCID
|
DBLP
90
TITLE:
AN IC ARCHITECTURE FOR BOARD-LEVEL MIXED-SIGNAL TEST SUPPORT
AUTHORS:
FERREIRA, JC
; LEAO, AC;
DASILVA, JM
;
MATOS, JS
;
PUBLISHED:
1994
,
SOURCE:
7th Mediterranean Electrotechnical Conference (MeleCON 94)
in
7TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, VOLS 1-3,
VOLUME:
2
INDEXED IN:
Scopus
WOS
CrossRef
IN MY:
ORCID
|
ResearcherID
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