181
TÍTULO: Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion
AUTORES: Hector Pettenghi ; Leonel Sousa ; Jude Angelo Ambrose;
PUBLICAÇÃO: 2012, FONTE: 17th Asia and South Pacific Design Automation Conference (ASP-DAC) in 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)
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182
TÍTULO: Energy Efficient Stream-based Configurable Architecture for Embedded Platforms
AUTORES: Frederico Pratas; Pedro Tomas ; Pedro Trancoso; Leonel Sousa ;
PUBLICAÇÃO: 2012, FONTE: International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (IC-SAMOS) in 2012 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS (SAMOS): ARCHITECTURES, MODELING AND SIMULATION
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184
TÍTULO: Fine-grain parallelism using multi-core, Cell/BE, and GPU systems  Full Text
AUTORES: Pratas, F; Trancoso, P; Sousa, L ; Stamatakis, A; Shi, G; Kindratenko, V;
PUBLICAÇÃO: 2012, FONTE: Parallel Computing, VOLUME: 38, NÚMERO: 8
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185
TÍTULO: Hierarchical partitioning algorithm for scientific computing on highly heterogeneous CPU + GPU clusters
AUTORES: Clarke, D; Ilic, A ; Lastovetsky, A; Sousa, L ;
PUBLICAÇÃO: 2012, FONTE: 18th International Conference on Parallel Processing, Euro-Par 2012 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 7484 LNCS
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186
TÍTULO: High performance unified architecture for forward and inverse quantization in H.264/AVC
AUTORES: Dias, T; Rosario, L; Roma, N ; Sousa, L ;
PUBLICAÇÃO: 2012, FONTE: 15th Euromicro Conference on Digital System Design, DSD 2012 in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
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187
TÍTULO: MRC-Based RNS Reverse Converters for the Four-Moduli Sets {2(n)+1, 2(n)-1, 2(n), 2(2n+1)-1} and {2(n)+1, 2(n)-1, 2(2n), 2(2n+1)-1}
AUTORES: Leonel Sousa ; Samuel Antao;
PUBLICAÇÃO: 2012, FONTE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 59, NÚMERO: 4
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188
TÍTULO: MRC-Based RNS Reverse Converters for the Four-Moduli Sets {2(n)+1, 2(n)-1, 2(n), 2(2n+1)-1} and {2(n)+1, 2(n)-1, 2(2n), 2(2n+1)-1} (vol 59, pg 244, 2012)
AUTORES: Leonel Sousa ; Samuel Antao;
PUBLICAÇÃO: 2012, FONTE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 59, NÚMERO: 5
INDEXADO EM: WOS
189
TÍTULO: Multi-level Parallelization of Advanced Video Coding on Hybrid CPU+GPU Platforms
AUTORES: Svetislav Momcilovic ; Nuno Roma ; Leonel Sousa ;
PUBLICAÇÃO: 2012, FONTE: Parallel Processing Workshops, Euro-Par 2012: BDMC 2012, CGWS 2012, HeteroPar 2012, HiBB 2012, OMHI 2012, Paraphrase 2012, PROPER 2012, Resilience 2012, UCHPC 2012, VHPC 2012 in Euro-Par 2012: Parallel Processing Workshops - BDMC, CGWS, HeteroPar, HiBB, OMHI, Paraphrase, PROPER, Resilience, UCHPC, VHPC, Rhodes Islands, Greece, August 27-31, 2012. Revised Selected Papers, VOLUME: 7640
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190
TÍTULO: On realistic divisible load scheduling in highly heterogeneous distributed systems
AUTORES: Ilic, A ; Sousa, L ;
PUBLICAÇÃO: 2012, FONTE: 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2012 in Proceedings - 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2012
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