261
TÍTULO: Insertion of irregular-shaped logos in the compressed DCT domain
AUTORES: Roma, N ; Sousa, L ;
PUBLICAÇÃO: 2002, FONTE: 14th International Conference on Digital Signal Processing (DSP 2002) in DSP 2002: 14TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING PROCEEDINGS, VOLS 1 AND 2, VOLUME: 1
INDEXADO EM: Scopus WOS CrossRef
262
TÍTULO: Video coding by using the 3D zero-tree approach in the wavelet transform domain
AUTORES: Salvado, J; Sousa, L ;
PUBLICAÇÃO: 2002, FONTE: 14th International Conference on Digital Signal Processing (DSP 2002) in DSP 2002: 14TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING PROCEEDINGS, VOLS 1 AND 2, VOLUME: 2
INDEXADO EM: Scopus WOS CrossRef
263
TÍTULO: A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
AUTORES: Nuno Roma ; Leonel Sousa ;
PUBLICAÇÃO: 2001, FONTE: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, VOLUME: 218
INDEXADO EM: DBLP CrossRef
NO MEU: DBLP
264
TÍTULO: A platform independent parallelising tool based on graph theoretic models
AUTORES: Sinnen, O; Sousa, L ;
PUBLICAÇÃO: 2001, FONTE: 4th International Conference on Vector and Parallel Processing (VECPAR 2000) in VECTOR AND PARALLEL PROCESSING - VECPAR 2000, VOLUME: 1981
INDEXADO EM: WOS
265
TÍTULO: Comparison of contention aware list scheduling heuristics for cluster computing
AUTORES: Sinnen, O; Sousa, L ;
PUBLICAÇÃO: 2001, FONTE: 30th International Conference on Parallel Processing (ICPP Workshops) in INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, VOLUME: 2001-January
INDEXADO EM: Scopus WOS DBLP CrossRef
266
TÍTULO: Exploiting Unused Time Slots in List Scheduling Considering Communication Contention
AUTORES: Oliver Sinnen; Leonel Sousa ;
PUBLICAÇÃO: 2001, FONTE: Euro-Par 2001: Parallel Processing, 7th International Euro-Par Conference Manchester, UK August 28-31, 2001, Proceedings, VOLUME: 2150
INDEXADO EM: DBLP CrossRef
NO MEU: DBLP
267
TÍTULO: Parameterizable hardware architectures for automatic synthesis of motion estimation processors
AUTORES: Roma, N ; Sousa, L ;
PUBLICAÇÃO: 2001, FONTE: IEEE Workshop on Signal Processing, Systems Design and Implementation (SiPS 01) in SIPS 2001: IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION
INDEXADO EM: Scopus WOS
268
TÍTULO: Scheduling task graphs on arbitrary processor architectures considering contention
AUTORES: Sinnen, O; Sousa, L ;
PUBLICAÇÃO: 2001, FONTE: 9th International Conference on High-Performance Computing and Networking in HIGH-PERFORMANCE COMPUTING AND NETWORKING, VOLUME: 2110
INDEXADO EM: Scopus WOS DBLP CrossRef
269
TÍTULO: Synchronous non-local image processing on Orthogonal Multiprocessor Systems
AUTORES: Sousa, L ; Sinnen, O;
PUBLICAÇÃO: 2001, FONTE: 4th International Conference on Vector and Parallel Processing (VECPAR 2000) in VECTOR AND PARALLEL PROCESSING - VECPAR 2000, VOLUME: 1981
INDEXADO EM: Scopus WOS
270
TÍTULO: A Platform Independent Parallelising Tool Based on Graph Theoretic Models
AUTORES: Oliver Sinnen; Leonel Sousa ;
PUBLICAÇÃO: 2000, FONTE: Vector and Parallel Processing - VECPAR 2000, 4th International Conference, Porto, Portugal, June 21-23, 2000, Selected Papers and Invited Talks, VOLUME: 1981
INDEXADO EM: Scopus DBLP CrossRef
NO MEU: ORCID | DBLP
Página 27 de 29. Total de resultados: 283.