Mário Pereira Véstias
AuthID: R-000-CZ3
71
TÃTULO: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTORES: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2015, FONTE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, NÚMERO: 1
AUTORES: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2015, FONTE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, NÚMERO: 1
INDEXADO EM: 
Scopus 
WOS
Scopus WOS NO MEU: 
ORCID
ORCID72
TÃTULO: A Many-Core Co-Processor for Embedded Parallel Computing on FPGA
AUTORES: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTORES: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
73
TÃTULO: Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture
AUTORES: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTORES: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
74
TÃTULO: Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA
AUTORES: Tiago Rodrigues; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTORES: Tiago Rodrigues; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
75
TÃTULO: FPGA-based Architecture for Hyperspectral Unmixing
AUTORES: Nascimento, JMP; Vestias, M; Martin, G;
PUBLICAÇÃO: 2015, FONTE: IEEE International Geoscience and Remote Sensing Symposium (IGARSS) in 2015 IEEE INTERNATIONAL GEOSCIENCE AND REMOTE SENSING SYMPOSIUM (IGARSS)
AUTORES: Nascimento, JMP; Vestias, M; Martin, G;
PUBLICAÇÃO: 2015, FONTE: IEEE International Geoscience and Remote Sensing Symposium (IGARSS) in 2015 IEEE INTERNATIONAL GEOSCIENCE AND REMOTE SENSING SYMPOSIUM (IGARSS)
INDEXADO EM: WOS
WOS NO MEU: ORCID
ORCID76
TÃTULO: Enhancing stochastic computations via process variation
AUTORES: Duarte, RP; Véstias, M; Neto, H;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications, FPL 2015 in 25th International Conference on Field Programmable Logic and Applications, FPL 2015
AUTORES: Duarte, RP; Véstias, M; Neto, H;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications, FPL 2015 in 25th International Conference on Field Programmable Logic and Applications, FPL 2015
77
TÃTULO: FPGA-based architecture for hyperspectral unmixing
AUTORES: Nascimento, JMP; Vestias, M; Martin, G;
PUBLICAÇÃO: 2015, FONTE: IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2015 in International Geoscience and Remote Sensing Symposium (IGARSS), VOLUME: 2015-November
AUTORES: Nascimento, JMP; Vestias, M; Martin, G;
PUBLICAÇÃO: 2015, FONTE: IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2015 in International Geoscience and Remote Sensing Symposium (IGARSS), VOLUME: 2015-November
78
TÃTULO: Enhancing Stochastic Computations via Process Variation
AUTORES: Rui Policarpo Duarte; Mario Vestias; Horacio Neto;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
AUTORES: Rui Policarpo Duarte; Mario Vestias; Horacio Neto;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
INDEXADO EM: WOS
WOS NO MEU: ORCID
ORCID79
TÃTULO: Efficient implementation of a single-precision floating-point arithmetic unit on FPGA
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
80
TÃTULO: Trends of CPU, GPU and FPGA for high-performance computing
AUTORES: Vestias, M; Neto, H;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
AUTORES: Vestias, M; Neto, H;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
