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TÍTULO: Run-time generation of partial FPGA configurations for subword operations  Full Text
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2012, FONTE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 36, NÚMERO: 5
INDEXADO EM: Scopus WOS DBLP CrossRef
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TÍTULO: Run-time generation of partial FPGA configurations  Full Text
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2012, FONTE: JOURNAL OF SYSTEMS ARCHITECTURE, VOLUME: 58, NÚMERO: 1
INDEXADO EM: Scopus WOS DBLP CrossRef: 2
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TÍTULO: Run-time Generation of Partial Configurations for Arithmetic Expressions  Full Text
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2010, FONTE: 53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010) in 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS
INDEXADO EM: Scopus WOS CrossRef
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TÍTULO: Creation of Partial FPGA Configurations at Run-Time
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2010, FONTE: 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools in 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS
INDEXADO EM: Scopus WOS DBLP CrossRef: 4
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TÍTULO: GENERATION OF PARTIAL FPGA CONFIGURATIONS AT RUN-TIME
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2008, FONTE: International Conference on Field Programmable and Logic Applications in 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2
INDEXADO EM: Scopus WOS DBLP CrossRef: 15
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TÍTULO: Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems  Full Text
AUTORES: Silva, ML; Ferreira, JC ;
PUBLICAÇÃO: 2007, FONTE: 20th International Conference on Design of Ciruits and Integrated Systems in IET COMPUTERS AND DIGITAL TECHNIQUES, VOLUME: 1, NÚMERO: 5
INDEXADO EM: Scopus WOS DBLP CrossRef: 7
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TÍTULO: Support for partial run-time reconfiguration of platform FPGAs  Full Text
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2006, FONTE: JOURNAL OF SYSTEMS ARCHITECTURE, VOLUME: 52, NÚMERO: 12
INDEXADO EM: Scopus WOS DBLP CrossRef: 20
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TÍTULO: Exploiting dynamic reconfiguration of platform FPGAs: implementation issues
AUTORES: Silva, ML; João Canas Ferreira ;
PUBLICAÇÃO: 2006, FONTE: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, VOLUME: 2006
INDEXADO EM: Scopus DBLP CrossRef: 3
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TÍTULO: Using a tightly-coupled pipeline in dynamically reconfigurable platform FPGAs
AUTORES: Silva, ML; Ferreira, JC ;
PUBLICAÇÃO: 2005, FONTE: 8th Euromicro Conference on Digital System Design in DSD 2005: 8th Euromicro Conference on Digital System Design, Proceedings, VOLUME: 2005
INDEXADO EM: Scopus WOS DBLP CrossRef
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TÍTULO: Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer
AUTORES: João Canas Ferreira ; Miguel M Silva;
PUBLICAÇÃO: 2005, FONTE: 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 in 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, VOLUME: 2005
INDEXADO EM: Scopus DBLP CrossRef: 4