José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
11
TITLE: SIREN. a depth-first search algorithm for the filter design optimization problem
AUTHORS: Levent Aksoy; Paulo Flores; José Monteiro;
PUBLISHED: 2013, SOURCE: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13
AUTHORS: Levent Aksoy; Paulo Flores; José Monteiro;
PUBLISHED: 2013, SOURCE: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13
12
TITLE: Design and Characterization of a QLUT in a Standard CMOS Process
AUTHORS: Diogo Brito; Jorge Fernandes; Paulo Flores; Jose Monteiro;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
AUTHORS: Diogo Brito; Jorge Fernandes; Paulo Flores; Jose Monteiro;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXED IN: 
WOS
WOS13
TITLE: Efficient Area and Power Multiplication Part of FFT Based on Twiddle Factor Decomposition
AUTHORS: Sidinei Ghissoni; Eduardo Costa; Jose Monteiro; Ricardo Reis;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
AUTHORS: Sidinei Ghissoni; Eduardo Costa; Jose Monteiro; Ricardo Reis;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXED IN: WOS
WOS14
TITLE: Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs
AUTHORS: Levent Aksoy; Eduardo Costa; Paulo Flores; Jose Monteiro;
PUBLISHED: 2012, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)
AUTHORS: Levent Aksoy; Eduardo Costa; Paulo Flores; Jose Monteiro;
PUBLISHED: 2012, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)
INDEXED IN: WOS
WOS15
TITLE: Hardware Implementation of a Centroid-based Localization Algorithm for Mobile Sensor Networks
AUTHORS: Leonardo L Oliveira; Gustavo F Dessbesell; Joao B Martins; Jose Monteiro;
PUBLISHED: 2011, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
AUTHORS: Leonardo L Oliveira; Gustavo F Dessbesell; Joao B Martins; Jose Monteiro;
PUBLISHED: 2011, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: WOS
WOS16
TITLE: CentroidM. a centroid-based localization algorithm for mobile sensor networks
AUTHORS: Leonardo Londero de Oliveira; João Baptista Martins; Gustavo Fernando Dessbesell; José Monteiro;
PUBLISHED: 2010, SOURCE: Proceedings of the 23rd symposium on Integrated circuits and system design - SBCCI '10
AUTHORS: Leonardo Londero de Oliveira; João Baptista Martins; Gustavo Fernando Dessbesell; José Monteiro;
PUBLISHED: 2010, SOURCE: Proceedings of the 23rd symposium on Integrated circuits and system design - SBCCI '10
17
TITLE: Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates
AUTHORS: Sidinei Ghissoni; Joao Batista D dos Santos Martins; Ricardo Augusto D da Luz Reis; Jose Carlos Monteiro;
PUBLISHED: 2010, SOURCE: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 5953
AUTHORS: Sidinei Ghissoni; Joao Batista D dos Santos Martins; Ricardo Augusto D da Luz Reis; Jose Carlos Monteiro;
PUBLISHED: 2010, SOURCE: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 5953
INDEXED IN: WOS
WOS18
TITLE: Analysis of the Conditions for Worst Case Switching Activity in Integrated Circuits
AUTHORS: Carlos Sampaio; Jose Monteiro; Silveira, L. Miguel;
PUBLISHED: 2010, SOURCE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
AUTHORS: Carlos Sampaio; Jose Monteiro; Silveira, L. Miguel;
PUBLISHED: 2010, SOURCE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
INDEXED IN: WOS
WOS19
TITLE: A New Quaternary FPGA Based on a Voltage-mode Multi-valued Circuit
AUTHORS: Cristiano Lazzari; Paulo Flores; Jose Monteiro; Luigi Carro;
PUBLISHED: 2010, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)
AUTHORS: Cristiano Lazzari; Paulo Flores; Jose Monteiro; Luigi Carro;
PUBLISHED: 2010, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)
INDEXED IN: WOS
WOS20
TITLE: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
AUTHORS: Lars Svensson; José Monteiro;
PUBLISHED: 2009, SOURCE: Lecture Notes in Computer Science
AUTHORS: Lars Svensson; José Monteiro;
PUBLISHED: 2009, SOURCE: Lecture Notes in Computer Science
