José João Henriques Teixeira de Sousa
AuthID: R-000-8D6
1
TITLE: A 1.7-mW-92-dBm Sensitivity Low-IF Receiver in 0.13-mu m CMOS for Bluetooth LE Applications
AUTHORS: Marco Silva Pereira; Jose T de Sousa; Joao Costa Freire; Joao Caldinhas Vaz;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOLUME: 67, ISSUE: 1
AUTHORS: Marco Silva Pereira; Jose T de Sousa; Joao Costa Freire; Joao Caldinhas Vaz;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOLUME: 67, ISSUE: 1
INDEXED IN: 
WOS
WOS2
TITLE: Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores
AUTHORS: Luis Fiolhais; Fernando Goncalves; Rui P Duarte; Mario Vestias; Jose T de Sousa;
PUBLISHED: 2019, SOURCE: IEEE International Symposium on Circuits and Systems (IEEE ISCAS) in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
AUTHORS: Luis Fiolhais; Fernando Goncalves; Rui P Duarte; Mario Vestias; Jose T de Sousa;
PUBLISHED: 2019, SOURCE: IEEE International Symposium on Circuits and Systems (IEEE ISCAS) in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: WOS
WOS3
TITLE: K-means clustering on CGRA
AUTHORS: Joao D Lopes; Jose T de Sousa; Horacio Neto; Mario Vestias;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTHORS: Joao D Lopes; Jose T de Sousa; Horacio Neto; Mario Vestias;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXED IN: WOS
WOS4
TITLE: A fast SAT Solver strategy based on negated clauses
AUTHORS: Romanelli Zuim; Jose T Sousa; Claudionor N Coelho;
PUBLISHED: 2006, SOURCE: International Conference on Very Large Scale Integration and System-on-Chip in IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP
AUTHORS: Romanelli Zuim; Jose T Sousa; Claudionor N Coelho;
PUBLISHED: 2006, SOURCE: International Conference on Very Large Scale Integration and System-on-Chip in IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP
INDEXED IN: WOS
WOS5
TITLE: LAYOUT-LEVEL TECHNIQUES FOR TESTABILITY IMPROVEMENT OF MOS PHYSICAL DESIGNS
AUTHORS: SANTOS, MB; GONCALVES, FM; SOUSA, JJT; TEIXEIRA, JP;
PUBLISHED: 1991, SOURCE: 6TH MEDITERRANEAN ELECTROTECHNICAL CONF ( MELECON 91 ) in 6TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, PROCEEDINGS VOLS 1 AND 2
AUTHORS: SANTOS, MB; GONCALVES, FM; SOUSA, JJT; TEIXEIRA, JP;
PUBLISHED: 1991, SOURCE: 6TH MEDITERRANEAN ELECTROTECHNICAL CONF ( MELECON 91 ) in 6TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, PROCEEDINGS VOLS 1 AND 2
INDEXED IN: WOS
WOS6
TITLE: High-quality physical designs of CMOS ICs
AUTHORS: Sousa, JJT; Goncalves, FM; Teixeira, JP;
PUBLISHED: 1991, SOURCE: Euro ASIC 1991 in Euro ASIC 1991
AUTHORS: Sousa, JJT; Goncalves, FM; Teixeira, JP;
PUBLISHED: 1991, SOURCE: Euro ASIC 1991 in Euro ASIC 1991
INDEXED IN: 
Scopus
Scopus