A Universal Architecture for Designing Efficient Modulo 2(N)+1 Multipliers (Vol 52, Pg 1166, 2005)

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 P-000-1K1
2
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Tipo de Documento
Correction
Year published
2005
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in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN: 1549-8328
Volume: 52, Número: 9, Páginas: 1982-1982 (1)
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DBLP: journals/tcas/SousaC05a
SCOPUS: 2-s2.0-27144539328
Wos: WOS:000232084300027
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ISSN: 1549-8328
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