A Universal Architecture for Designing Efficient Modulo 2(N)+1 Multipliers (Vol 52, Pg 1166, 2005)

AuthID
P-000-1K1
2
Author(s)
Document Type
Correction
Year published
2005
Published
in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN: 1549-8328
Volume: 52, Issue: 9, Pages: 1982-1982 (1)
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Publication Identifiers
Dblp: journals/tcas/SousaC05a
Scopus: 2-s2.0-27144539328
Wos: WOS:000232084300027
Source Identifiers
ISSN: 1549-8328
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