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Dynamic Partial Reconfiguration of Customized Single-Row Accelerators
AuthID
P-00P-S0Y
3
Author(s)
Paulino, NMC
·
Ferreira, JC
·
Cardoso, JMP
Document Type
Article
Year published
2019
Published
in
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
ISSN: 1063-8210
Volume: 27, Issue: 1, Pages: 116-125 (10)
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Dblp
®
/pt/publications/view/746526
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7
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Publication Identifiers
DOI
:
10.1109/tvlsi.2018.2874079
Dblp
: journals/tvlsi/PaulinoFC19
Wos
: WOS:000455117600012
Source Identifiers
ISSN
: 1063-8210
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