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Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

AuthID
P-008-A38

Author(s)

Paulino, N

Ferreira, JC

Cardoso, JMP

Editor(s)

Brisk, P; Coutinho, JGD; Diniz, PC

Document Type

Proceedings Paper

Year published

2013

Published

in RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS in Lecture Notes in Computer Science, ISSN: 0302-9743

Volume: 7806, Pages: 122-133 (12)

Conference

9Th International Applied Reconfigurable Computing Symposium (Arc), Date: MAR 25-27, 2013, Location: Los Angeles, CA, Sponsors: Univ So Calif, Informat Sci Inst

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Publication Identifiers

DOI: 10.1007/978-3-642-36812-7_12

Dblp: conf/arc/PaulinoFC13

Scopus: 2-s2.0-84875535021

Wos: WOS:000342984500012

Source Identifiers

ISSN: 0302-9743

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Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

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