José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
21
TÃTULO: Combination of radix-2<sup>m</sup> multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers
AUTORES: Leandro Zafalon Pieper; Eduardo A C da Costa; Jose C Monteiro;
PUBLICAÇÃO: 2013, FONTE: 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)
AUTORES: Leandro Zafalon Pieper; Eduardo A C da Costa; Jose C Monteiro;
PUBLICAÇÃO: 2013, FONTE: 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)
22
TÃTULO: Design and Characterization of a QLUT in a Standard CMOS Process
AUTORES: Diogo Brito; Jorge Fernandes; Paulo Flores; Jose Monteiro;
PUBLICAÇÃO: 2012, FONTE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
AUTORES: Diogo Brito; Jorge Fernandes; Paulo Flores; Jose Monteiro;
PUBLICAÇÃO: 2012, FONTE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXADO EM: 
WOS
WOS23
TÃTULO: Efficient Area and Power Multiplication Part of FFT Based on Twiddle Factor Decomposition
AUTORES: Sidinei Ghissoni; Eduardo Costa; Jose Monteiro; Ricardo Reis;
PUBLICAÇÃO: 2012, FONTE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
AUTORES: Sidinei Ghissoni; Eduardo Costa; Jose Monteiro; Ricardo Reis;
PUBLICAÇÃO: 2012, FONTE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXADO EM: WOS
WOS24
TÃTULO: Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs
AUTORES: Levent Aksoy; Eduardo Costa; Paulo Flores; Jose Monteiro;
PUBLICAÇÃO: 2012, FONTE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)
AUTORES: Levent Aksoy; Eduardo Costa; Paulo Flores; Jose Monteiro;
PUBLICAÇÃO: 2012, FONTE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)
INDEXADO EM: WOS
WOS25
TÃTULO: Power macro-modeling using an iterative LS-SVM method
AUTORES: Gusmão, A; Silveira, L. Miguel ; Monteiro, J;
PUBLICAÇÃO: 2011, FONTE: 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009 in IFIP Advances in Information and Communication Technology, VOLUME: 360
AUTORES: Gusmão, A; Silveira, L. Miguel ; Monteiro, J;
PUBLICAÇÃO: 2011, FONTE: 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009 in IFIP Advances in Information and Communication Technology, VOLUME: 360
26
TÃTULO: Hardware Implementation of a Centroid-based Localization Algorithm for Mobile Sensor Networks
AUTORES: Leonardo L Oliveira; Gustavo F Dessbesell; Joao B Martins; Jose Monteiro;
PUBLICAÇÃO: 2011, FONTE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
AUTORES: Leonardo L Oliveira; Gustavo F Dessbesell; Joao B Martins; Jose Monteiro;
PUBLICAÇÃO: 2011, FONTE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXADO EM: WOS
WOS27
TÃTULO: Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
AUTORES: Levent Aksoy; Eduardo Costa; Paulo Flores; Jose Monteiro;
PUBLICAÇÃO: 2010, FONTE: 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
AUTORES: Levent Aksoy; Eduardo Costa; Paulo Flores; Jose Monteiro;
PUBLICAÇÃO: 2010, FONTE: 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
28
TÃTULO: CentroidM. a centroid-based localization algorithm for mobile sensor networks
AUTORES: Leonardo Londero de Oliveira; João Baptista Martins; Gustavo Fernando Dessbesell; José Monteiro;
PUBLICAÇÃO: 2010, FONTE: Proceedings of the 23rd symposium on Integrated circuits and system design - SBCCI '10
AUTORES: Leonardo Londero de Oliveira; João Baptista Martins; Gustavo Fernando Dessbesell; José Monteiro;
PUBLICAÇÃO: 2010, FONTE: Proceedings of the 23rd symposium on Integrated circuits and system design - SBCCI '10
29
TÃTULO: Analysis of the conditions for worst case switching activity in integrated circuits
AUTORES: Sampaio, C; Monteiro, J; Silveira, L. Miguel ;
PUBLICAÇÃO: 2010, FONTE: 1st IEEE Latin American Symposium on Circuits and Systems, LASCAS 2010 in Proceedings - 2010 1st IEEE Latin American Symposium on Circuits and Systems, LASCAS 2010
AUTORES: Sampaio, C; Monteiro, J; Silveira, L. Miguel ;
PUBLICAÇÃO: 2010, FONTE: 1st IEEE Latin American Symposium on Circuits and Systems, LASCAS 2010 in Proceedings - 2010 1st IEEE Latin American Symposium on Circuits and Systems, LASCAS 2010
30
TÃTULO: Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates
AUTORES: Sidinei Ghissoni; Joao Batista D dos Santos Martins; Ricardo Augusto D da Luz Reis; Jose Carlos Monteiro;
PUBLICAÇÃO: 2010, FONTE: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 5953
AUTORES: Sidinei Ghissoni; Joao Batista D dos Santos Martins; Ricardo Augusto D da Luz Reis; Jose Carlos Monteiro;
PUBLICAÇÃO: 2010, FONTE: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 5953
INDEXADO EM: WOS
WOS