Toggle navigation
Publicações
Investigadores
Instituições
0
Entrar
Autenticação Federada
(Click on the image)
Autenticação local
Recuperação de Password
Register
Entrar
Publicações
Procurar
Estatísticas
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
AuthID
P-00A-4B4
3
Author(s)
Paulino, N
·
Ferreira, JC
·
Cardoso, JMP
Document Type
Article
Year published
2015
Published
in
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS,
ISSN: 1936-7406
Volume: 7, Issue: 4, Pages: 29:1-29:20 (20)
Indexing
Wos
®
Scopus
®
Dblp
®
/pt/publications/view/332132
Crossref
®
3
Google Scholar
®
Metadata
Sources
Publication Identifiers
DOI
:
10.1145/2629468
Dblp
: journals/trets/PaulinoFC15
Scopus
: 2-s2.0-84911387509
Wos
: WOS:000350529900002
Source Identifiers
ISSN
: 1936-7406
Export Publication Metadata
Export
×
Publication Export Settings
BibTex
EndNote
APA
Export Preview
Lista
Marked
Adicionar à lista
Marked
Info
At this moment we don't have any links to full text documens.
×
Select Source
This publication has:
2 records from
ISI
2 records from
SCOPUS
2 records from
DBLP
2 records from
Unpaywall
Please select which records must be used by Authenticus!
×
Preview Publications
© 2024 CRACS & Inesc TEC - All Rights Reserved
Privacy Policy
|
Terms of Service