João Paulo Cacho Teixeira


AuthID: R-000-7A4

Confirmed Publications: 110



81
TITLE: On identifying and evaluating object architectures for real-time applications  Full Text
AUTHORS: Dias, OP; Teixeira, IM ; Teixeira, JP ; Becker, LB; Pereira, CE;
PUBLISHED: 2001, SOURCE: 6th IFAC Workshop on Algorithms and Architectures for Real-Time Control (AARTC 2000) in CONTROL ENGINEERING PRACTICE, VOLUME: 9, ISSUE: 4
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
82
TITLE: RTL-based functional test generation for high defects coverage in digital systems  Full Text
AUTHORS: Santos, MB ; Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2001, SOURCE: IEEE European Test Workshop in JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, VOLUME: 17, ISSUE: 3-4
INDEXED IN: Scopus WOS CrossRef: 7
IN MY: ORCID
83
TITLE: Low power BIST by filtering non-detecting vectors  Full Text
AUTHORS: Manich, S; Gabarro, A; Lopez, M; Figueras, J; Girard, P; Guiller, L; Landrault, C; Pravossoudovitch, S; Teixeira, P ; Santos, M ;
PUBLISHED: 2000, SOURCE: 6th IEEE International O-Line Testing Workshop in JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, VOLUME: 16, ISSUE: 3
INDEXED IN: Scopus WOS CrossRef: 19
IN MY: ORCID
84
TITLE: Defect-oriented sampling of non-equally probable faults in VLSI systems  Full Text
AUTHORS: Goncalves, FM ; Teixeira, JP ;
PUBLISHED: 1999, SOURCE: Proceedings of the 1998 16th IEEE VLSI Test Symposium, (VTS 98): Test Innovations for Highly Complex, High Speed, Deep Submicron IC's in JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, VOLUME: 15, ISSUE: 1-2
INDEXED IN: Scopus WOS CrossRef: 4
IN MY: ORCID
85
TITLE: Defect-Oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique  Full Text
AUTHORS: Santos, MB ; Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1999, SOURCE: 17th IEEE Very Large Scale Intergration Test Symposium in 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
86
TITLE: Defect-oriented testing of analogue and mixed signal ICs
AUTHORS: Santos, MB ; Goncalves, FM ; Ohletz, M; Teixeira, JP ;
PUBLISHED: 1998, SOURCE: Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
INDEXED IN: Scopus
IN MY: ORCID
87
TITLE: Detect-oriented test quality assessment using fault sampling and simulation  Full Text
AUTHORS: Goncalves, FM ; Santos, MB ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1998, SOURCE: International Test Conference 1998 in INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
88
TITLE: Sampling techniques of non-equally probable faults in VLSI systems  Full Text
AUTHORS: Goncalves, FM ; Teixeira, JP ;
PUBLISHED: 1998, SOURCE: 16th IEEE VLSI Symposium in 16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
89
TITLE: Realistic fault extraction for high-quality design and test of VLSI systems
AUTHORS: Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1997, SOURCE: 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems in 1997 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
90
TITLE: Defect-oriented IC test and diagnosis using VHDL fault simulation  Full Text
AUTHORS: Celeiro, F; Dias, L; Ferreira, J; Santos, MB; Teixeira, JP ;
PUBLISHED: 1996, SOURCE: 1996 International Test Conference (ITC 1996) - Test and Design Validity in INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
Página 9 de 11. Total de resultados: 110.

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