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TITLE: A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP  Full Text
AUTHORS: Ferlini, Frederico; Viel, Felipe; Seman, Laio Oriel; Pettenghi, Hector; Bezerra, Eduardo Augusto; Leithardt, Valderi Reis Quietinho;
PUBLISHED: 2023, SOURCE: ELECTRONICS, VOLUME: 12, ISSUE: 4
INDEXED IN: Scopus WOS CrossRef
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TITLE: Towards the Integration of Reverse Converters into the RNS Channels
AUTHORS: Leonel Sousa; Rogerio Paludo; Paulo Martins; Hector Pettenghi;
PUBLISHED: 2020, SOURCE: IEEE TRANSACTIONS ON COMPUTERS, VOLUME: 69, ISSUE: 3
INDEXED IN: Scopus WOS
3
TITLE: Method for designing two levels RNS reverse converters for large dynamic ranges  Full Text
AUTHORS: Hector Pettenghi; Ricardo Chaves ; Roberto de Matos; Leonel Sousa ;
PUBLISHED: 2016, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 55
INDEXED IN: Scopus WOS DBLP CrossRef
4
TITLE: RNS Reverse Converters based on the New Chinese Remainder Theorem I
AUTHORS: Hector Pettenghi; Leonel Sousa ;
PUBLISHED: 2015, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLUME: 2015-July
INDEXED IN: Scopus WOS DBLP CrossRef
5
TITLE: Novel methodology to improve Multi-moduli architectures for Binary-to-RNS conversion
AUTHORS: Pettenghi, H; Sousa, L ; Ambrose, JA;
PUBLISHED: 2015, SOURCE: Conference on Design of Circuits and Integrated Systems, DCIS 2015 in 2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015
INDEXED IN: Scopus CrossRef
6
TITLE: Novel methodology to improve Multi-moduli architectures for Binary-to-RNS conversion
AUTHORS: Hector Pettenghi; Leonel Sousa ; Jude Angelo Ambrose;
PUBLISHED: 2015, SOURCE: 2015 Conference on Design of Circuits and Integrated Systems (DCIS) in 2015 Conference on Design of Circuits and Integrated Systems (DCIS)
INDEXED IN: WOS
7
TITLE: EFFICIENT METHOD FOR DESIGNING MODULO {2(n) +/- k} MULTIPLIERS  Full Text
AUTHORS: Hector Pettenghi; Sorin Cotofana; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, VOLUME: 23, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef
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TITLE: Method for designing Multi-Channel RNS Architectures to prevent Power Analysis SCA
AUTHORS: Hector Pettenghi; Jude Angelo Ambrose; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: Scopus WOS DBLP CrossRef
9
TITLE: Method for Designing Efficient Mixed Radix Multipliers  Full Text
AUTHORS: Pettenghi, H; Pratas, F; Sousa, L ;
PUBLISHED: 2014, SOURCE: CIRCUITS SYSTEMS AND SIGNAL PROCESSING, VOLUME: 33, ISSUE: 10
INDEXED IN: Scopus WOS DBLP CrossRef
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TITLE: DARNS: A Randomized Multi-modulo RNS Architecture for Double-and-Add in ECC to prevent Power Analysis Side Channel Attacks
AUTHORS: Jude Angelo Ambrose; Hector Pettenghi; Leonel Sousa;
PUBLISHED: 2013, SOURCE: 18th Asia and South Pacific Design Automation Conference (ASP-DAC) in 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)
INDEXED IN: WOS
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