Nuno Miguel Cardanha Paulino


AuthID: R-002-RAV

Confirmed Publications: 41



31
TITLE: Dynamic Partial Reconfiguration of Customized Single-Row Accelerators  Full Text
AUTHORS: Paulino, NMC ; Ferreira, JC ; Cardoso, JMP ;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 27, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 7
IN MY: ORCID | DBLP | CIÊNCIAVITAE
32
TITLE: Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces  Full Text
AUTHORS: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 25, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 6
IN MY: ORCID | DBLP | CIÊNCIAVITAE
33
TITLE: On Coding Techniques for Targeting FPGAs via OpenCL
AUTHORS: Nuno Paulino ; Luís Reis; João M P Cardoso ;
PUBLISHED: 2017, SOURCE: Parallel Computing is Everywhere, Proceedings of the International Conference on Parallel Computing, ParCo 2017, 12-15 September 2017, Bologna, Italy, VOLUME: 32
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID | DBLP
34
35
TITLE: A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses  Full Text
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2015, SOURCE: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, VOLUME: 7, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 3
IN MY: ORCID | DBLP | CIÊNCIAVITAE
36
TITLE: Transparent Acceleration of Program Execution Using Reconfigurable Hardware  Full Text
AUTHORS: Paulino, N ; Ferreira, JC ; Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2015, SOURCE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
INDEXED IN: Scopus WOS DBLP CrossRef: 6
IN MY: ORCID | DBLP | CIÊNCIAVITAE
37
TITLE: Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2014, SOURCE: 12th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA) in 2014 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS (ISPA)
INDEXED IN: Scopus WOS DBLP CrossRef: 4
IN MY: ORCID | DBLP | CIÊNCIAVITAE
38
TITLE: Architecture for Transparent Binary Acceleration of Loops with Memory Accesses  Full Text
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2013, SOURCE: 9th International Applied Reconfigurable Computing Symposium (ARC) in RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, VOLUME: 7806
INDEXED IN: Scopus WOS DBLP CrossRef: 2
IN MY: ORCID | DBLP | CIÊNCIAVITAE
39
TITLE: Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units  Full Text
AUTHORS: Bispo, J ; Paulino, N ; Cardoso, JMP ; Ferreira, JC ;
PUBLISHED: 2013, SOURCE: International Journal of Reconfigurable Computing, VOLUME: 2013
INDEXED IN: Scopus DBLP CrossRef: 6
IN MY: ORCID | DBLP | CIÊNCIAVITAE
40
TITLE: Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
AUTHORS: Joao Bispo ; Nuno Paulino ; Joao M P Cardoso ; Joao C Ferreira ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOLUME: 9, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef: 10
IN MY: ORCID | DBLP | CIÊNCIAVITAE
Page 4 of 5. Total results: 41.

footer slogan

Useful Links

Get Help

© 2025 CRACS & Inesc TEC - All Rights Reserved Privacy Policy | Terms of Service