Nuno Miguel Cardanha Paulino


AuthID: R-002-RAV

Confirmed Publications: 33



21
TITLE: Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey  Full Text
AUTHORS: Nuno Paulin ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2020, SOURCE: ACM COMPUTING SURVEYS, VOLUME: 53, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 5
IN MY: ORCID | DBLP
22
TITLE: Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets
AUTHORS: Paulino, N ; Ferreira, JC ; Cardoso, JMP ;
PUBLISHED: 2020, SOURCE: IEEE ACCESS, VOLUME: 8
INDEXED IN: Scopus WOS DBLP CrossRef: 1
IN MY: ORCID | DBLP
23
TITLE: Dynamic Partial Reconfiguration of Customized Single-Row Accelerators  Full Text
AUTHORS: Paulino, NMC ; Ferreira, JC ; Cardoso, JMP ;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 27, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
24
TITLE: Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces  Full Text
AUTHORS: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 25, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 6
IN MY: ORCID | DBLP
25
TITLE: On Coding Techniques for Targeting FPGAs via OpenCL
AUTHORS: Nuno Paulino ; Luís Reis; João M P Cardoso ;
PUBLISHED: 2017, SOURCE: Parallel Computing is Everywhere, Proceedings of the International Conference on Parallel Computing, ParCo 2017, 12-15 September 2017, Bologna, Italy, VOLUME: 32
INDEXED IN: Scopus DBLP
IN MY: ORCID | DBLP
26
27
TITLE: A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses  Full Text
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2015, SOURCE: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, VOLUME: 7, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 3
IN MY: ORCID | DBLP
28
TITLE: Transparent Acceleration of Program Execution Using Reconfigurable Hardware  Full Text
AUTHORS: Paulino, N ; Ferreira, JC ; Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2015, SOURCE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
INDEXED IN: Scopus WOS DBLP CrossRef: 6
IN MY: ORCID | DBLP
29
TITLE: Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2014, SOURCE: 12th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA) in 2014 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS (ISPA)
INDEXED IN: Scopus WOS DBLP CrossRef: 4
IN MY: ORCID | DBLP
30
TITLE: Architecture for Transparent Binary Acceleration of Loops with Memory Accesses  Full Text
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2013, SOURCE: 9th International Applied Reconfigurable Computing Symposium (ARC) in RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, VOLUME: 7806
INDEXED IN: Scopus WOS DBLP CrossRef: 2
IN MY: ORCID | DBLP
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